The latches mode of overflow of ALU resolved by bit 2 in the register of the mode and the status of the processor (MSTAT) leads to that the flag of overflow of AV remains lifted after overflow in spite of the fact that the subsequent instructions can not generate overflow. In this mode the flag of AV can be cleared only by direct recording of zero via the tire DMD.
It is the simplest form of record; 16 bits make a line of bits. Examples of operations in which this format is used, the logical operations NOT,AND,OR,XOR are. These operations executed by ALU consider that their arguments of a line of bits and do not care of a sign or of the provision of a decimal point
Results of multiplication represent bit lines. Operands are processed as it is specified in the instruction (multiplication sign, multiplication bezznakovy, multiplication sign on bezznakovy or rounding operation). the 32-bit result from the multiplier is considered sign as there is a sign expansion on all 40 bits of sets of the register of the multiplier (MR).
For obtaining simpler scheme ALU algorithms of arithmetic and logical operations should be chosen from a condition of receiving the minimum set of microoperations. Thus it is necessary to consider the requirement of ensuring the set speed of ALU: too limited set of microoperations can lead to "long microprograms of some operations" that increases time of performance of these operations.
All devices in processors of this family of the 16 bit with the fixed point. Almost all operations mean representation of sign numbers in the form of addition to two. The others use bezznakovy numbers or simply lines of bits. Special support is available for verbose calculations and block floating arithmetics.
The operating memory is a part of the central control unit and belongs to the class of constant memory. This type of memory is used for storage of microprograms. It is distinguished by very high speed and the small capacity which is defined by quantity of teams in system of commands of the central processor.
All arithmetic-logic operations treat the operands and receive results as 16 digit bit lines, except for primitives of sign division (DIVS). Various flags treat results as numbers with a sign: flag of overflow (AV) and flag of a negative number (AN).
The most advanced achievements of engineering thought are embodied in microprocessors - the most difficult microelectronic devices-. In the conditions of peculiar this branch of production of fierce competition and huge capital investments, release of each new model of the microprocessor - is anyway connected with the next scientific, design, technological break.
The greatest specialization and a variety of functions the microcontrollers used in the built-in control systems including in household appliances possess. Total number of crystals with various systems of teams exceeds 500, and all of them, owing to existence of products with their use, have the steady share of the market.
Modules of random access and constant memory, are connected with the microprocessor directly. Other devices (the monitor, the keyboard, stores on magnetic carriers, etc.) are connected with the microprocessor via controlers of input-output which, in turn, are connected with the microprocessor via the system tire.
3 After summation the result sign is analyzed: if the result negative, it is inverted if positive - "+1" central processing unit is added to the younger category of result and the analysis of signs of overflow is made
ALU contains two sets of the registers AR, AF, AHO, AH1, AYO, AY V each timepoint the domain only one set. The additional set of registers can be made active (for example, when processing interruption) for very fast switching of contexts. The new task, such as interruption processing, can be executed without storing of current state of registers ALU.
Any registers connected with ALU can both be read, and to be written in one cycle. Registers are read at the beginning of a cycle and register at the end. The new value which is written down in the register cannot be schitano prior to the beginning of the following cycle.